DSPI.h

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#ifndef _DSPI_H
#define _DSPI_H

/*
 **************************************************************
 * Defines, Macros and Typedefs 
 **************************************************************/
/*** Constant Macros ***/
/* Default Yes and No defines */
#ifndef TRUE
#define TRUE (1u)
#endif
#ifndef CLEAR
#define CLEAR (0u)
#endif
#ifndef BITS_IN_NIBBLE
#define BITS_IN_NIBBLE (4u)
#endif
#ifndef BITS_IN_BYTE
#define BITS_IN_BYTE (8u)
#endif
#ifndef BITS_IN_32
#define BITS_IN_32  (32u)
#endif
#ifndef BITS_IN_16
#define BITS_IN_16  (16u)
#endif
#ifndef BYTES_IN_32
#define BYTES_IN_32  (4u)
#endif
#ifndef BYTES_IN_16
#define BYTES_IN_16  (2u)
#endif

#ifndef BIT_DEFINITION
#define BIT_DEFINITION
#define BIT0  (1u << 0u)
#define BIT1  (1u << 1u)
#define BIT2  (1u << 2u)
#define BIT3  (1u << 3u)
#define BIT4  (1u << 4u)
#define BIT5  (1u << 5u)
#define BIT6  (1u << 6u)
#define BIT7  (1u << 7u)
#define BIT8  (1u << 8u)
#define BIT9  (1u << 9u)
#define BIT10 (1u << 10)
#define BIT11 (1u << 11)
#define BIT12 (1u << 12)
#define BIT13 (1u << 13)
#define BIT14 (1u << 14)
#define BIT15 (1u << 15)
#define BIT16 (1u << 16)
#define BIT17 (1u << 17)
#define BIT18 (1u << 18)
#define BIT19 (1u << 19)
#define BIT20 (1u << 20)
#define BIT21 (1u << 21)
#define BIT22 (1u << 22)
#define BIT23 (1u << 23)
#define BIT24 (1u << 24)
#define BIT25 (1u << 25)
#define BIT26 (1u << 26)
#define BIT27 (1u << 27)
#define BIT28 (1u << 28)
#define BIT29 (1u << 29)
#define BIT30 (1u << 30)
#define BIT31 (1u << 31)
#endif

/* For information */
#define N_DSPI_PRESETS   (8u)
#define N_DSPI_INSTANCES (4u)

/* Defines below are used to configure different instances of DSPIs */
#define DSPI0C0 (0x00)
#define DSPI0C1 (0x01)
#define DSPI0C2 (0x02)
#define DSPI0C3 (0x03)
#define DSPI0C4 (0x04)
#define DSPI0C5 (0x05)
#define DSPI0C6 (0x06)
#define DSPI0C7 (0x07)

#define DSPI1C0 (0x10)
#define DSPI1C1 (0x11)
#define DSPI1C2 (0x12)
#define DSPI1C3 (0x13)
#define DSPI1C4 (0x14)
#define DSPI1C5 (0x15)
#define DSPI1C6 (0x16)
#define DSPI1C7 (0x17)

#define DSPI2C0 (0x20)
#define DSPI2C1 (0x21)
#define DSPI2C2 (0x22)
#define DSPI2C3 (0x23)
#define DSPI2C4 (0x24)
#define DSPI2C5 (0x25)
#define DSPI2C6 (0x26)
#define DSPI2C7 (0x27)

#define DSPI3C0 (0x30)
#define DSPI3C1 (0x31)
#define DSPI3C2 (0x32)
#define DSPI3C3 (0x33)
#define DSPI3C4 (0x34)
#define DSPI3C5 (0x35)
#define DSPI3C6 (0x36)
#define DSPI3C7 (0x37)

/* Following are masks for Preset Configs */
/* MSW */
#define DSPI_CPOL_SET   (0x80000000u)
#define DSPI_CPOL_CLEAR (0x00000000u)
#define DSPI_CPHA_SET   (0x40000000u)
#define DSPI_CPHA_CLEAR (0x00000000u)
#define DSPI_LSB_FIRST  (0x20000000u)
#define DSPI_MSB_FIRST  (0x00000000u)
#define DSPI_16_BIT     (0x1E000000u)
#define DSPI_9_BIT      (0x10000000u)
#define DSPI_8_BIT      (0x0E000000u)
#define DSPI_DBR_SET    (0x01000000u)
#define DSPI_DBR_CLEAR  (0x00000000u)
#define DSPI_BRP_0      (0x00000000u)
#define DSPI_BRP_1      (0x00400000u)
#define DSPI_BRP_2      (0x00800000u)
#define DSPI_BRP_3      (0x00C00000u)
#define DSPI_BR_0       (0x00000000u)
#define DSPI_BR_1       (0x00040000u)
#define DSPI_BR_2       (0x00080000u)
#define DSPI_BR_3       (0x000C0000u)
#define DSPI_BR_4       (0x00100000u)
#define DSPI_BR_5       (0x00140000u)
#define DSPI_BR_6       (0x00180000u)
#define DSPI_BR_7       (0x001C0000u)
#define DSPI_BR_8       (0x00200000u)
#define DSPI_BR_9       (0x00240000u)
#define DSPI_BR_A       (0x00280000u)
#define DSPI_BR_B       (0x002C0000u)
#define DSPI_BR_C       (0x00300000u)
#define DSPI_BR_D       (0x00340000u)
#define DSPI_BR_E       (0x00380000u)
#define DSPI_BR_F       (0x003C0000u)
#define DSPI_PCSSCK_00  (0x00000000u)
#define DSPI_PCSSCK_01  (0x00010000u)
#define DSPI_PCSSCK_10  (0x00020000u)
#define DSPI_PCSSCK_11  (0x00030000u)
#define DSPI_CCSCK_0    (0x00000000u)
#define DSPI_CCSCK_1    (0x00001000u)
#define DSPI_CCSCK_2    (0x00002000u)
#define DSPI_CCSCK_3    (0x00003000u)
#define DSPI_CCSCK_4    (0x00004000u)
#define DSPI_CCSCK_5    (0x00005000u)
#define DSPI_CCSCK_6    (0x00006000u)
#define DSPI_CCSCK_7    (0x00007000u)
#define DSPI_CCSCK_8    (0x00008000u)
#define DSPI_CCSCK_9    (0x00009000u)
#define DSPI_CCSCK_A    (0x0000A000u)
#define DSPI_CCSCK_B    (0x0000B000u)
#define DSPI_CCSCK_C    (0x0000C000u)
#define DSPI_CCSCK_D    (0x0000D000u)
#define DSPI_CCSCK_E    (0x0000E000u)
#define DSPI_CCSCK_F    (0x0000F000u)
/* LSW */
#define DSPI_PDT_00  (0x00000000u)
#define DSPI_PDT_01  (0x40000000u)
#define DSPI_PDT_10  (0x80000000u)
#define DSPI_PDT_11  (0xC0000000u)
#define DSPI_DT_0    (0x00000000u)
#define DSPI_DT_1    (0x04000000u)
#define DSPI_DT_2    (0x08000000u)
#define DSPI_DT_3    (0x0C000000u)
#define DSPI_DT_4    (0x10000000u)
#define DSPI_DT_5    (0x14000000u)
#define DSPI_DT_6    (0x18000000u)
#define DSPI_DT_7    (0x1C000000u)
#define DSPI_DT_8    (0x20000000u)
#define DSPI_DT_9    (0x24000000u)
#define DSPI_DT_A    (0x28000000u)
#define DSPI_DT_B    (0x2C000000u)
#define DSPI_DT_C    (0x30000000u)
#define DSPI_DT_D    (0x34000000u)
#define DSPI_DT_E    (0x38000000u)
#define DSPI_DT_F    (0x3C000000u)
#define DSPI_PASC_00 (0x00000000u)
#define DSPI_PASC_01 (0x01000000u)
#define DSPI_PASC_10 (0x02000000u)
#define DSPI_PASC_11 (0x03000000u)
#define DSPI_ASC_0   (0x00000000u)
#define DSPI_ASC_1    (0x00100000u)
#define DSPI_ASC_2    (0x00200000u)
#define DSPI_ASC_3    (0x00300000u)
#define DSPI_ASC_4    (0x00400000u)
#define DSPI_ASC_5    (0x00500000u)
#define DSPI_ASC_6    (0x00600000u)
#define DSPI_ASC_7    (0x00700000u)
#define DSPI_ASC_8    (0x00800000u)
#define DSPI_ASC_9    (0x00900000u)
#define DSPI_ASC_A    (0x00A00000u)
#define DSPI_ASC_B    (0x00B00000u)
#define DSPI_ASC_C    (0x00C00000u)
#define DSPI_ASC_D    (0x00D00000u)
#define DSPI_ASC_E    (0x00E00000u)
#define DSPI_ASC_F    (0x00F00000u)

/* Following are masks for overal config of SPI instances */
#define DSPI_DISABLE        (0x80000000u)
#define DSPI_ENABLE         (0x00000000u)
#define DSPI_IS_MASTER      (0x40000000u)
#define DSPI_IS_SLAVE       (0x00000000u)
#define DSPI_CONT_CLK_EN    (0x20000000u)
#define DSPI_CONT_CLK_DIS   (0x00000000u)
#define DSPI_TX_FIFO_DIS    (0x10000000u)
#define DSPI_TX_FIFO_EN     (0x00000000u)
#define DSPI_RX_FIFO_DIS    (0x08000000u)
#define DSPI_RX_FIFO_EN     (0x00000000u)
#define DSPI_TX_ISR_EN      (0x04000000u)
#define DSPI_TX_ISR_DIS     (0x00000000u)
#define DSPI_TX_DMA_EN      (0x02000000u)
#define DSPI_TX_DMA_DIS     (0x00000000u)
#define DSPI_RX_ISR_EN      (0x01000000u)
#define DSPI_RX_ISR_DIS     (0x00000000u)
#define DSPI_RX_DMA_EN      (0x00800000u)
#define DSPI_RX_DMA_DIS     (0x00000000u)
#define DSPI_CS7_INVERT_EN  (0x00400000u)
#define DSPI_CS7_INVERT_DIS (0x00000000u)
#define DSPI_CS6_INVERT_EN  (0x00200000u)
#define DSPI_CS6_INVERT_DIS (0x00000000u)
#define DSPI_CS5_INVERT_EN  (0x00100000u)
#define DSPI_CS5_INVERT_DIS (0x00000000u)
#define DSPI_CS4_INVERT_EN  (0x00080000u)
#define DSPI_CS4_INVERT_DIS (0x00000000u)
#define DSPI_CS3_INVERT_EN  (0x00040000u)
#define DSPI_CS3_INVERT_DIS (0x00000000u)
#define DSPI_CS2_INVERT_EN  (0x00020000u)
#define DSPI_CS2_INVERT_DIS (0x00000000u)
#define DSPI_CS1_INVERT_EN  (0x00010000u)
#define DSPI_CS1_INVERT_DIS (0x00000000u)
#define DSPI_CS0_INVERT_EN  (0x00008000u)
#define DSPI_CS0_INVERT_DIS (0x00000000u)
#define DSPI_MODIFIED_TIME_DIS (0x00000000u)

/* Delay between transfers - set for 625 nsec using a 64MHz sys clock */
#define DSPI_DELAY_POST_TRANSFER (4u)
#define DSPI_PDT_DEFAULT         (3u)

/* Delay between last clock and CS going high set to 350 nsec w. 64MHz clock */
#define DSPI_DELAY_AFTER_SCK     (2u)
#define DSPI_PRESCALER_AFTER_SCK (1u)

/* Register masks */
#define DSPI_SR_TXRXS_MASK        ((uint32_t)BIT28)
#define DSPI_FIFO_BUFFER_DEPTH    (5u)

#define PUSHR_EOQ_MASK      ((uint32_t)BIT27)

#define DSPI_FULL_TRANSFER_BITS (16u)

/* For use in u8fnDSPISwitchIsrMode */
#define DSPI_ENABLE_DMA_DISABLE_ISR (0x01u)
#define DSPI_DISABLE_DMA_ENABLE_ISR (0x00u)

/*** Function Macros ***/
/* Macro below is meant to replace u32fnFormatDSPIPUSHR */
#define FORMAT_PUSHR(XX, YY, ZZ, AA, BB) \
  ((uint32_t)BB | (uint32_t)(YY << 16u) | \
      (uint32_t)((XX & 0x0Fu) << 28u) | (uint32_t)(ZZ << 31u) | \
      (uint32_t)((AA & 0x01) << 27u))


/*** Enums ***/
enum INSTANCE_INDEX
{
  INDEX_I0C0 = 0, INDEX_I0C1, INDEX_I0C2, INDEX_I0C3, INDEX_I0C4, INDEX_I0C5,
  INDEX_I0C6, INDEX_I0C7, INDEX_I1C0, INDEX_I1C1, INDEX_I1C2, INDEX_I1C3,
  INDEX_I1C4, INDEX_I1C5, INDEX_I1C6, INDEX_I1C7, INDEX_I2C0, INDEX_I2C1,
  INDEX_I2C2, INDEX_I2C3, INDEX_I2C4, INDEX_I2C5, INDEX_I2C6, INDEX_I2C7,
  INDEX_I3C0, INDEX_I3C1, INDEX_I3C2, INDEX_I3C3, INDEX_I3C4, INDEX_I3C5,
  INDEX_I3C6, INDEX_I3C7
};

enum DSPI_STATUS
{
  DSPI_STATUS_CLEAR = 0u, DSPI_BUSY_WITH_PREVIOUS_TX, DSPI_NOT_HALTED
};

/*** TypeDefs ***/
typedef union
{
  struct
  {
    vuint8_t ContCSEn :1; /* 1 */ 
    vuint8_t Instance :3; /* 4 */
    vuint8_t CTAR :4; /* 8 */
  } P;
  
  vuint8_t W;
} DSPIInstance_t;
typedef union
{
  struct
  {
    vuint32_t CPol :1; /* 1 */
    vuint32_t CPhase :1; /* 2 */
    vuint32_t LSBFirst :1; /* 3 */
    vuint32_t FrameSize :4; /* 7 */
    /* BR = Sys/PBR * (1 + DBR) / BR */
    vuint32_t BaudRateDoubler :1; /* 8 */
    vuint32_t BaudRatePrescaler :2; /* 10 */
    vuint32_t BaudRate :4; /* 14 */
    /* tCSC = (PCSSCK * CSSCK) / fSYS */
    vuint32_t PCSSCK :2; /* 16 */
    vuint32_t CSSCK :4; /* 20 */
    vuint32_t ReservedForFutureUse :4; /* 24 */
    DSPIInstance_t MyDSPI; /* 32 */
    vuint32_t DelayAfterTransferPrescaler: 2u; /* 34 */
    vuint32_t DelayAfterTransfer: 4u; /* 38 */
    vuint32_t LagAfterLastClkPrescaler: 2u; /* 40 */
    vuint32_t LagAfterLastClk: 4u; /* 44u */
    vuint32_t Reserved: 20u; /* 64 */
  } P;
  struct
  {
    vuint32_t MSW;
    vuint32_t LSW;
  } W;
} DSPIPresetConfig_t;

typedef union
{
  struct
  {
    vuint32_t Disable :1; /* Disable the whole module */ /* 1 */
    vuint32_t Mode :1; /* 1 = Master, 0 = Slave, */ /* 2 */
    vuint32_t ContClock :1; /* 3 */
    vuint32_t TxFIFODis :1; /* 4 */
    vuint32_t RxFIFODis :1; /* 5 */
    vuint32_t ISRTxEn :1; /* 6 */
    vuint32_t ISRTxDMAEn :1; /* 7 */
    vuint32_t ISRRxEn :1; /* 8 */
    vuint32_t ISRRxDMAEn :1; /* 9 */
    vuint32_t CS7HiWhenInactive :1; /* 10 */
    vuint32_t CS6HiWhenInactive :1; /* 11 */
    vuint32_t CS5HiWhenInactive :1; /* 12 */
    vuint32_t CS4HiWhenInactive :1; /* 13 */
    vuint32_t CS3HiWhenInactive :1; /* 14 */
    vuint32_t CS2HiWhenInactive :1; /* 15 */
    vuint32_t CS1HiWhenInactive :1; /* 16 */
    vuint32_t CS0HiWhenInactive :1; /* 17 */
    vuint32_t Reserved :7; /* 24 */
    DSPIInstance_t MyDSPI; /* 32 */
  } P;
  
  vuint16_t W;
} DSPIConfig_t;

typedef volatile struct DSPI_tag* DSPI_t;
/*
 **************************************************************
 * Declarations 
 **************************************************************/
/*** Constants ***/
extern const uint8_t cau8DSPIInstances[N_DSPI_INSTANCES * N_DSPI_PRESETS];
extern const DSPI_t catDSPIInstances[N_DSPI_INSTANCES];
/*** Globals ***/
extern vuint8_t gau8DSPIBuffSize[N_DSPI_INSTANCES];
extern vuint8_t gau8DSPIWordsRx[N_DSPI_INSTANCES];
extern vuint8_t gau8DSPITransferSize[N_DSPI_INSTANCES];
extern vuint8_t gau8DSPITxFIFOIsEnabled[N_DSPI_INSTANCES];
extern vuint8_t gau8DSPIRxFIFOIsEnabled[N_DSPI_INSTANCES];

/* Globals for 16-bit transfers */
extern vuint16_t* gpu16DSPITxBuffer[N_DSPI_INSTANCES];
extern vuint16_t* gpu16DSPIRxBuffer[N_DSPI_INSTANCES];
/* Globals for 8-bit transfers */
extern vuint8_t* gpu8DSPITxBuffer[N_DSPI_INSTANCES];
extern vuint8_t* gpu8DSPIRxBuffer[N_DSPI_INSTANCES];

/*** Static Globals ***/

/*
 ******************************************************************************
 * Function Prototypes 
 *****************************************************************************/
/*
 ******************************************************************************
 *
 * Function:          u8fnDSPITranscieve()
 *
 */
uint8_t u8fnDSPITranscieve(const uint8_t u8MyInstance,
                           const uint8_t u8CSEnable, uint16_t* pu16DSPITx,
                           uint16_t* pu16DSPIRx, const uint8_t u8Size);
/*
 ******************************************************************************
 *
 * Function:          u32fnDSPIStatus()
 *
 */
uint32_t u32fnDSPIStatus(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPIEnable()
 *
 */
void vfnDSPIEnable(const DSPIInstance_t tMyInstance, const uint8_t u8CSEnable,
                   const uint8_t u8Start);
/*
 ******************************************************************************
 *
 * Function:          u8fnConfigDSPIGeneral()
 *
 */
uint8_t u8fnConfigDSPIGeneral(const DSPIConfig_t* tDSPIConfig);
/*
 ******************************************************************************
 *
 * Function:          u8fnConfigDSPIPreset()
 *
 */
uint8_t u8fnConfigDSPIPreset(const DSPIPresetConfig_t* tDSPIConfig);
/*
 ******************************************************************************
 *
 * Function:          u8fnIsDSPIBusy()
 *
 */
uint8_t u8fnIsDSPIBusy(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          u8fnMailboxAppendToDSPIOutbox()
 *
 */
uint32_t u32fnFormatDSPIPUSHR(uint8_t u8DSPIInstance, uint8_t u8CS,
                              uint8_t u8ContCS, uint8_t u8EndOfQueueFlag,
                              uint16_t u16Msg);
/*
 ******************************************************************************
 *
 * Function:          u8fnDSPISwitchIsrMode()
 *
 */
uint8_t u8fnDSPISwitchIsrMode(uint8_t u8DSPIInstance, uint8_t u8IsrMode);
/*
 ******************************************************************************
 *
 * Function:          vfnGenericDSPIFUFISR()
 *
 */
static void vfnGenericDSPIFUFISR(DSPI_t tpActiveDSPI);
/*
 ******************************************************************************
 *
 * Function:          vfnGenericDSPITCFIsr()
 *
 */
static void vfnGenericDSPITCFIsr(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          vfnGenericDSPIEOQIsr()
 *
 */
static void vfnGenericDSPIEOQIsr(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          vfnGenericDSPIRFDFIsr()
 *
 */
static void vfnGenericDSPIRFDFIsr(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          vfnGenericDSPITFFFIsr()
 *
 */
static void vfnGenericDSPITFFFIsr(uint8_t u8Instance);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI0FUFIsr()
 *
 */
void vfnDSPI0FUFISR(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI1FUFIsr()
 *
 */
void vfnDSPI1FUFISR(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI2FUFIsr()
 *
 */
void vfnDSPI2FUFISR(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI3FUFIsr()
 *
 */
void vfnDSPI3FUFISR(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI0TCFIsr()
 *
 */
void vfnDSPI0TCFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI1TCFIsr()
 *
 */
void vfnDSPI1TCFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI2TCFIsr()
 *
 */
void vfnDSPI2TCFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI3TCFIsr()
 *
 */
void vfnDSPI3TCFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI0EOQIsr()
 *
 */
void vfnDSPI0EOQIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI1EOQIsr()
 *
 */
void vfnDSPI1EOQIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI2EOQIsr()
 *
 */
void vfnDSPI2EOQIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI3EOQIsr()
 *
 */
void vfnDSPI3EOQIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI0RFDFIsr()
 *
 */
void vfnDSPI0RFDFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI1RFDFIsr()
 *
 */
void vfnDSPI1RFDFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI2RFDFIsr()
 *
 */
void vfnDSPI2RFDFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI3RFDFIsr()
 *
 */
void vfnDSPI3RFDFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI0TFFFIsr()
 *
 */
void vfnDSPI0TFFFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI1TFFFIsr()
 *
 */
void vfnDSPI1TFFFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI2TFFFIsr()
 *
 */
void vfnDSPI2TFFFIsr(void);
/*
 ******************************************************************************
 *
 * Function:          vfnDSPI3TFFFIsr()
 *
 */
void vfnDSPI3TFFFIsr(void);
#endif /* _FILENAME_H */